1. Technical Field
This invention relates to systems and methods for multiple-phase clock generation.
2. Description of the Background
Digital circuitry is being used in applications requiring seemingly ever faster processing speeds. For example, complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) devices have been used to sample high-frequency carrier-modulated signals in order to recover the data in such signals, often as part of a communications device. Because the frequency of the signals is sometimes far in excess of the speeds capable of any individual CMOS device, the signals are oversampled by arrays of similar sampling circuitry clocked by multiple-phase (xe2x80x9cmulti-phasexe2x80x9d) clocks in order to simulate a single much faster device. Oversampling of such high-speed signals makes it possible to use comparatively slow CMOS devices for high-speed applications such as communications and computing by using multiple-phase clocks to process high-speed signals in parallel. Correspondingly, as the underlying signal frequency increases, the number of clock phases needed to accommodate the signal frequency increases.
In many devices today, ring oscillators are used to generate multiple-phase clocks. However, this technique suffers from a number of disadvantages in the environment just described. More specifically, the quality of a multi-phase clock degrades as the number of clock phases increases. Furthermore, generation of a larger number of multiple-phase clocks makes layout and routing more difficult in an integrated circuit chip.
Another technique used to generate multi-phase clocks employs cascaded voltage-controlled oscillator (xe2x80x9cVCOxe2x80x9d) cell stages. Like the ring-oscillator, the number of waveform samplers is the same as the number of VCO cells. Also like the ring-oscillator, as cells are added the precision of the multi-phase clock degrades, thereby placing a practical limit on how many cells can be added. For example, in FIG. 1 there is shown a prior art schematic diagram having cascaded ring-oscillator-type VCO cells. To increase the number of phases corresponding to an increased number of samplers, the number of VCO cells must also increase by adding more stages into the ring. In general, the number of VCO stages rises proportionally with the increasing frequency of the waveform to be received. However, as the number of VCO cells increases, the power consumption and layout area necessary for multiple-phase bus routing also increase. As a result, the optimum layout of a VCO and other sampling circuitry becomes increasingly difficult as the number of cells increases.
Another technique used is clock interpolation, which generates more phases from a given multi-phase clock. For example, in FIG. 2 there is shown a prior art schematic diagram having a clock interpolator circuit. Unfortunately, this technique generates phase errors in the interpolated clocks. For example, if a clock interpolator receives two clock signals, clock A and clock B, the resulting output becomes the interpolated values of clock A and clock B. Unfortunately, this technique generates errors which makes such an interpolated clock signal deviate from the ideal value. If the clock phases have short rise/fall times then the interpolated value would deviate from the ideal value. This is because the inputs of clock interpolator are already in non-linear region at the interpolation time. This makes interpolator deviate from ideal location because the linear rule is no longer valid. If the clock phases for the clock interpolator have bigger rise/fall times then the interpolated value is very close to ideal value, however, this increases the effect of offsets and noise in the interpolating circuit, which would eventually degrade the quality of signals generated by an associated phase-locked loop (xe2x80x9cPLLxe2x80x9d). Also, if the clock edges are too sharp, the interpolated clock signal would not be an exact interpolation of the other phases used. To compensate for the noise increase, the power consumption of this device may be increased, but at the expense of eventually increasing the power consumption of the total system in which the device is embedded. Therefore, to realize a wide range of operations using clock interpolation, the circuit complexity and power consumption becomes impractical at some point.
Therefore, it would be desirable to have system and method for generating a multi-phase clock that mitigates the deleterious effects inherent in other multi-phase clocks as additional phases are generated.